| Topic | Post | Video |
|---|---|---|
| Computer architecture (overview, abstraction layers) | Layers of Abstraction in Computer System | Layers of Abstraction in Computing |
| Instruction set architecture (ISA) (programmer’s view of the machine) | Instruction set architecture - Wikipedia | What is Instruction Set Architecture ISA |
| Microarchitecture vs architecture | What is difference between architecture and microarchitecture? | What is the Difference Between Architecture and Microarchitecture? |
| Topic | Post | Video |
|---|---|---|
| Binary number | binary - What is “two’s complement”? | Binary Numbers and Two’s Complement |
| Two’s complement | Two’s Complement | Two’s Complement Explained |
| Floating-point arithmetic | IEEE 754 Floating Point Representations and Arithmetic | IEEE 754 Standard for Floating Point Binary Arithmetic |
| IEEE 754 | IEEE Standard for Floating-Point Arithmetic (IEEE 754) | IEEE Standard for Floating-Point Arithmetic (IEEE 754) |
| Endianness | Endianness: Big-Endian & Little-Endian | Endianness: Big-Endian & Little-Endian |
| Topic | Post | Video |
|---|---|---|
| Assembly language basics | Guide to x86 Assembly | Introduction to Assembly Language Tutorial |
| Machine code | RISC versus CISC | RISC vs CISC - Is it Still a Thing? |
| RISC vs CISC | Reduced instruction set computer - Wikipedia | RISC versus CISC |
| Example ISAs: x86 | A fundamental introduction to x86 assembly programming | Intro to x86 Assembly Language (Part 1) |
| ARM architecture | The Ultimate Guide to ISA in Microprocessors | The ARM University Program, ARM Architecture Fundamentals |
| Topic | Post | Video | ||||
|---|---|---|---|---|---|---|
| Central processing unit (CPU) | CPU, ALU, CU, and Registers | CPU 3: Hardware for ALU operations | ||||
| Control unit | [Design of CPU | Registers of CPU | Micro-operation and ALU](https://www.youtube.com/watch?v=ICWD1qEIrdg) | [Design of CPU | Registers of CPU | Micro-operation and ALU](https://www.youtube.com/watch?v=ICWD1qEIrdg) |
| Arithmetic logic unit (ALU) | Arithmetic logic unit - Wikipedia | 0052: ALU Design & Flags Registers Build | ||||
| Registers | Guide to x86 Assembly | CPU 3: Hardware for ALU operations | ||||
| Pipelining | what is difference between Superscaling and pipelining? | Lec 17: Advanced Pipelining & Superscalar Processors | ||||
| Superscalar architecture | Superscalar processor - Wikipedia | Lec 17: Advanced Pipelining & Superscalar Processors | ||||
| Out-of-order execution | What is general difference between Superscalar and out-of-order (OoO) execution? | Lec 17: Advanced Pipelining & Superscalar Processors | ||||
| Branch predictor | Branch predictor: How many “if”s are too many? | Branch Predictors: Introduction |
| Topic | Post | Video | ||
|---|---|---|---|---|
| Memory hierarchy | 5.1: Memory Hierarchy | Cache Hierarchy: How Modern CPU Caches Are Organized (L1, L2 and L3) | ||
| Cache (computing) – L1/L2/L3 caches, associativity, replacement policies | CPU cache - Wikipedia | Difference Between L1 L2 and L3 Cache Memory | ||
| Virtual memory | Virtual Memory, Page Tables And Translation Lookaside Buffers Explained | Virtual Memory, Page Tables And Translation Lookaside Buffers Explained | ||
| Paging, Translation lookaside buffer (TLB) | Translation lookaside buffer - Wikipedia | [4.4 TLB | Virtual Memory | Solved Problems](https://www.youtube.com/watch?v=7KkvQBLy1AE) |
| Random-access memory (RAM) basics | Computer Memory Types: DRAM, RAM Modules, DIMM/SO‑DIMM Basics | Understanding how RAM works how Memory is created internally |
| Topic | Post | Video |
|---|---|---|
| I/O (computing) concepts | I/O Interface (Interrupt and DMA Mode) | Polling/Interrupt/DMA differences explained easily |
| Interrupt | dma vs interrupt-driven i/o | Interrupt Driven I/O and Direct Memory Access(DMA) |
| Direct memory access (DMA) | Direct Memory Access (DMA) and Interrupt Handling | Polling/Interrupt/DMA differences explained easily |
| Topic | Post | Video |
|---|---|---|
| Instruction-level parallelism | Instruction-level parallelism - Wikipedia | Lecture 19: Instruction Level Parallelism – SMT |
| Multicore processor | Thread Level Parallelism - an overview | Thread Level Parallelism – SMT and CMP |
| Simultaneous multithreading (SMT) | Simultaneous multithreading - Wikipedia | Lecture 19: Instruction Level Parallelism – SMT |
| Parallel computing basics | The Ultimate Guide to Parallel Computing Basics and Models | Understanding Parallel Computing |
| Topic | Post | Video |
|---|---|---|
| Computer performance metrics | Computer Organization - Amdahl’s law and its proof | Amdahl’s Law in COA: Basics, Proof, and CPU Performance Explained |
| Amdahl’s law | Amdahl’s law - Wikipedia | Understanding Parallel Computing: Amdahl’s Law |
| Benchmark (computing) | Benchmark (computing) - Wikipedia | NVIDIA Blackwell Raises Bar in New InferenceMAX Benchmarks |
| Topic | Post | Video |
|---|---|---|
| Computer bus (e.g., PCIe) | Cache Coherent Interconnect for Accelerators (CCIX) | COHERENT MEMORY DEVICES OVER PCIe |
| Cache coherence | Question - PCIe Interconnect, RDMA, and Cache Coherence ? | Cache coherence protocol- Snoopy Bus Protocol |
| Memory-mapped I/O | Mastering Memory-Mapped I/O | Memory-mapped I/O in 8085 Microprocessor |
| Microprocessor history/evolution | Tracing the roots of the 8086 instruction set to the Datapoint 2200 minicomputer | Memory-mapped I/O and port-mapped I/O |